Field of the Invention
The present invention relates to a thin film transistor, a method for manufacturing the same, and a liquid crystal display panel and an electronic device using the same and more particularly to the thin film transistor suitably using a polycrystalline silicon as its semiconductor layer, the method for manufacturing the same, and the liquid crystal display panel and the electronic device using the thin film transistor.
Description of the Related Art
A semiconductor is used in a variety of technological applications and, for example, a thin film transistor (hereinafter simply, a “TFT”) using semiconductors makes up a pixel region and a driver circuit region of a liquid crystal display panel, thus contributing to improvement of display image quality and to thinning of the liquid crystal display panel.
The TFT of this type, for example, a p-Si (polycrystalline silicon) TFT, as shown in FIG. 22, when employed as a switching element of a liquid crystal display panel in a pixel region P for displaying pixels and in a circuit region C for driving elements, is formed on an insulating substrate such as a glass substrate 100. Generally, after a silicon oxide film is deposited first, as a backing insulating film 101, on the glass substrate 100, an a-Si (amorphous silicon) thin film is formed on the silicon oxide film and is crystallized to form a polycrystalline silicon thin film. Then, by performing etching process on the polycrystalline silicon thin film, active layers 102 of the TFT, which are activated in a post-process stage, are formed. After the formation of a gate insulating film 103 on the active layers 102 of the TFT, a gate electrode 104 made of metal, polycrystalline silicon, or the like is formed to obtain a basic structure of the TFT.
Next, an impurity is doped (or dosed) into the active layers 102 of the TFT by using the gate electrode 104 as a mask so that the impurity concentration therein becomes 1×1020/cm3. Thereafter, an annealing process is performed thereon to activate the impurity so that an activation rate of the doped impurity ordinarily becomes several tens of percent to form a source region (electrode) on one end of the active layer 102 and a drain region (electrode) on the other end of the active layer 102. Then, on the gate insulating film 103 and gate electrode 104 (including unillustrated gate wirings) is formed an interlayer insulating film 105. Next, by forming contact holes 107a passing through the interlayer insulating film 105 and the gate insulating film 103 on both sides of the gate electrode 104 to form wirings 107 (source and/or drain wirings) electrically connected to the active layers 102 (source and/or drain regions). Moreover, in FIG. 22, a pixel electrode 111 made of ITO (indium tin oxide), an orientation film 112, a liquid crystal layer 113, and a common electrode 114 also made of ITO (indium tin oxide) are shown.
In the polycrystalline silicon TFT having such a single drain structure as described above, large amounts of off-leakage currents flow even in an OFF state of the TFT and, therefore, if the above polycrystalline silicon TFT is used as a transistor for switching of a driver circuit or pixel of the liquid crystal display panel or the like, the reduction of the off-leakage currents is necessary. Especially, in the pixel region P where the above TFT is used as a pixel transistor, if the amount of the off-leakage currents is large, a malfunction occurs that electric charges cannot be held which causes a decrease in storage capacitance and degradation in display image quality. The off-leakage currents occur due to tunneling in a P-N junction at an end of the drain and, in the case of polycrystalline silicon, due to the existence many gap levels, tunneling occurs easily.
To solve such problems in the polycrystalline silicon TFT, various measures for the reduction of the off-leakage currents have been proposed. A method is disclosed in, for example, Japanese Patent No. 3143102 (Patent Reference 1), in which an off-leakage current is reduced by lowering impurity concentration in source/drain regions to raise a potential barrier through which a carrier tunnels, that is, to relax the concentration of an electric field. Another method is disclosed in Japanese Patent No. 3937956 (Patent Reference 2) in which, in addition to the lowering of impurity concentration in source/drain regions to reduce the off-leakage currents, an ON-current is surely obtained by raising the impurity concentration only in the region directly under a contact hole formed for connection of wirings in source/drain regions. Still another method is disclosed in Japanese Patent Application Laid-open No. Hei 11-345978 (Patent Reference 3) in which an off-leakage current is reduced by interposing an intermediate concentration region between a high impurity concentration region and a low impurity concentration region in source/drain regions to form an excellent junction and generate effective potential barrier. Still another method is disclosed in Japanese Patent Application Laid-open No. 2005-223347 (Patent Reference 4) in which, in addition to the lowering of an impurity concentration in source/drain regions, an off-leakage current is reduced by implanting a hydrogen ion into source/drain regions so that the impurity concentration falls within a range of 6.0 ×1018/cm3 to 1.0×1020/cm3. Still another method is disclosed in Japanese Patent Application Laid-open No. 2003-197631 (Patent Reference 5) in which an off-leakage current is reduced not by lowering impurity concentration but by applying high-energy flash light or high-energy laser light to source/drain regions to form a highly activated region having a high impurity activation rate of 10% to 100%. Moreover, in the above Patent Reference 5, a method of forming a low activated region having a low impurity activation rate of less than 10% is also described, however, the low activated region is simply interposed between highly activated regions functioning as the source/drain regions and, as a result, the formation of the low activated region does not contribute to the reduction in the off-leakage currents.
However, the TFTs described in the above Patent References 1 to 5 have disadvantages in that the off-leakage current can be reduced in a dark state of the TFT, however, while the TFT is being exposed to light, sufficient reduction in the off-leakage current is impossible. Moreover, the off-leakage current flowing while the TFT is being exposed to light is hereinafter called a “light leakage current”. Therefore, the use of such TFTs as a switching element in a pixel region of a liquid crystal display panel causes the degradation in display image quality.
The TFT disclosed in the Patent Reference 2 also has a disadvantage in that, in addition to the process of doping impurities into the source/drain regions, processes of doping impurities in a high concentration through contact holes formed for wiring connection in the source/drain regions are required, thus causing a rise in manufacturing costs and a decrease in yield. Similarly, the TFT disclosed in the Patent Reference 3 has a disadvantage in that the process of doping impurities is required at every time when the intermediate impurity concentration region is formed between the high impurity concentration region and low impurity concentration region in the source/drain regions, which also causes a rise in manufacturing costs and a decrease in yield.
The TFT disclosed in the Patent Reference 4 also has a disadvantage in that the process of not additionally doping impurities but newly doping hydrogen ions is required, also causing a rise in manufacturing costs and a decrease in yield.
Further, the TFT disclosed in the Patent Reference 5 has a disadvantage in that the process of not additionally doping impurities but applying high-energy light by spending considerable time is required, as a result, causing a rise in manufacturing costs and a decrease in yield.